In a groundbreaking announcement, Synopsys has unveiled the industry’s first complete PCIe 7.0 IP solution, which includes controllers, IDE security modules, PHY, and verification IP. This development comes at a time when PCIe 5.0 is still gaining traction in the market. The verification IP is already available, while the PCIe 7.0 controller—featuring IDE security functions—and PHY IP are slated for full launch in early 2025.

Compared to its predecessor, this IP solution promises to enhance interconnect power efficiency by up to 50%, while doubling the interconnect bandwidth at the same chip perimeter. Notably, Synopsys’ PCIe 7.0 PHY IP is designed to provide excellent signal integrity, supporting channel speeds of up to 128 Gb/s. This improvement is crucial for the reliability of high-speed data transfer, particularly as the technology landscape shifts towards faster and more efficient solutions.

The integration of card edge connectors plays a vital role in this context. These connectors facilitate seamless connections between the PCIe 7.0 devices and motherboards, ensuring that the increased data rates are effectively harnessed. The design and quality of the card edge connectors are critical, as they directly influence the performance and stability of the data transmission. As PCIe technology evolves, the demand for high-quality connectors that can handle greater speeds and minimize signal loss becomes even more pronounced.

This new offering has garnered strong support from several leading technology companies, including Intel, Astera Labs, Enfabrica, Kandou, Rivos, and Microchip. So, what exactly does PCIe 7.0 bring to the table?

First and foremost, it doubles the data rate, moving from PCIe 6.0’s 64 GT/s to an impressive 128 GT/s. To put this in perspective, a single lane can achieve a speed of 128 GT/s, equating to 16 GB/s. For an SSD that typically uses four lanes, this translates to a staggering 64 GB/s throughput. As PCIe 7.0 begins to emerge, the NAND transfer rate will no longer be a bottleneck, despite the current maximum of 3600 MT/s not being sufficient to support the new PCIe 7.0 speeds. Anticipation is building for the arrival of 4800 MT/s and 5600 MT/s NAND solutions to keep pace with these advancements.

However, the doubling of data rates poses significant challenges for electrical signal transmission. All PCBs inherently experience parasitic resistance, capacitance, and inductance. As data rates increase, the resulting high dV/dt can lead to substantial current flows in RCL circuits, which can cause oscillations and ultimately distort the signal, resulting in unacceptable data transmission error rates.

To address these challenges, PCI-SIG has revised the signal modulation method, transitioning from NRZ (Non-Return to Zero) to PAM4 (Pulse Amplitude Modulation) starting with PCIe 6.0. This shift aims to enhance the signal’s reliability and integrity in the face of ever-increasing data demands.

As the industry prepares for the rollout of PCIe 7.0, the implications for high-speed data transfer and the future of computing are profound. The performance enhancements driven by PCIe 7.0, along with the critical role of card edge connectors in facilitating these advancements, promise faster speeds and enhanced performance across a wide range of applications. With each iteration of PCIe technology, the need for robust and efficient connector solutions will be key to supporting the growing demands of modern computing environments.